When a trench is formed in a silicon (Si) substrate by a dry etching technique, the etching rate depends on a width of an opening of a mask. The dependence of the etching rate on the opening width of the mask is known as the “RIE-lag”. Due to the RIE-lag, it is difficult to simultaneously form trenches having the same depth and different widths in a Si substrate. FIG. 18 is a diagram illustrating a relationship between a depth of a trench and a width of an opening of a mask when the trench is formed by a dry etching technique using the mask. As can be seen from FIG. 18, the trench depth is almost constant in a range where the mask opening width is greater than a certain level. In contrast, the trench depth decreases with a decrease in the mask opening width in a range where the mask opening width is less than the certain level.
As disclosed, for example, in JP 2002-158214 A, it is possible to simultaneously form trenches having the same depth and different widths in a silicon-on-insulator (SOI) substrate. Since a buried oxide layer of the SOI substrate can serve as an etching stopper, the depths of trenches having different widths can be made equal by etching the trenches until the trenches reach the buried oxide layer.
However, since a SOI substrate is much more expensive than a Si substrate. Therefore, there is a need for a technique to form trenches having the same depth and different widths in a Si substrate. That is, there is a need for a technique to form trenches having different widths in a Si substrate by controlling the depths of the trenches independently.
In JP 2010-287823 A, which was filed by the present inventor, a double-layer structure passivation layer having an oxide layer and a polymer protection layer is formed on inner walls of trenches having different widths to reduce the RIE-lag so that the depths of the trenches can be made equal.
However, according to the method disclosed in JP 2010-287823 A, it is difficult to reduce the RIE-lag, if an aspect ratio of the trench is outside a certain RIE-lag reduction range. Further, since the passivation layer has a double-layer structure, manufacturing time is increased.
Specifically, as the etching depth become larger, it is more likely that the passivation layer remains on the bottom of the trench so that silicon needles (i.e., so-called “black silicon”) can be formed on the bottom of the trench. The present inventor conducted an experiment to measure the RIE-lag reduction range. FIG. 19 is a diagram illustrating a result of the experiment. As can be seen from FIG. 19, when the aspect ratio of the trench is greater than about 20, the depths of the trenches are not made equal, and the black silicon is formed in the trenches.
Further, since the passivation layer has a double-layer structure, there is a need to perform a step of forming a layer and a step of removing the layer for each layer of the passivation layer. As a result, the manufacturing time is increased.